1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device in which a word line discharging circuit is improved.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a portion of a conventional semiconductor memory device. In FIG. 1, there are provided a plurality of pairs of word lines, each pair being formed by a positive word line 1 and a negative word line 2, and there are also provided a plurality of pairs of bit lines, each pair being formed by a bit line 3 and a bit line 4. Memory cells 5 are connected at the respective points of intersection between the pairs of word lines and the pairs of bit lines. The memory cells 5 are selected by the pairs of word lines and the pairs of bit lines to store and read out information. A word line drive circuit 6 is connected to each positive word line 1. This word line drive circuit 6 drives the related positive word line 1 to be at a high potential when it is selected and drives it to be at a low potential when it is not selected. On the other hand, a current source 7 (the constant current value thereof being hereninafter represented as IH) is connected to each negative word line 2. The current source 7 stores and holds contents of the memory cells 5. The negative word lines 2 are connected to a current source 9 (a constant current value thereof being hereinafter represented as IDC) for discharging a word line through the respective diodes 8. The diodes 8 and the current source 9 constitute a word line discharging circuit 10.
If a certain pair of word lines changes from a selected state to a non selected state, another pair of word lines changes from a non selected state to a selected state. At this time, if a potential of the word lines changing from the selected state to the non selected state falls slowly, the word lines are temporarily brought into a double selected state. As a result, if information is to be read out, a delay is caused in detection of stored information to be read out and if information is to be written, the information is written in the memory cell selected immediately before that change, causing erroneous operation. Therefore, for the purposes of reading out information at high speed and preventing erroneous writing, the potential of the word lines changing from the selected state to the non selected state need to fall rapidly.
In the word line discharging circuit 10 shown in FIG. 1, the word line having the highest potential among the plurality of negative word lines 2 is connected to the current source 9 through the related diode 8. A word line 1 of a pair including the negative word line 2 having the highest potential is in a selected state. Consequently, if a certain pair of word lines changes from a selected state to a non selected state, the negative word line 2 of this pair is connected with both the current sources 7 and 9 and this word line 2 is discharged by current of IH + IDC. As a result, the potential of the word line falls rapidly.
However, the word line discharging circuit 10 shown in FIG. 1 involves the below described disadvantage because a discharging path is formed only for the negative word line 2 at the highest potential.
FIG. 2 shows changes in potential of a negative word line changing from a selected state to a non selected state and that of another negative word line changing from a non selected state to a selected state, the abscissa representing time and the ordinate representing potential of the negative word line. In FIG. 2, the line 21 shows potential of the negative word line changing from the selected state to the non selected state and the line 22 shows potential of the negative word line changing from the non selected state to the selected state. With respect to the point Q where the potentials of the negative word lines represented as the lines 21 and 22 are conincident, the potential of the negative word line represented as the line 21, changing from the selected state to the non selected state is no longer the highest potential after the point Q and the discharging current thereof changes from IH + IDC to simply IH. Accordingly, the line 21 falls slowly after the point Q as shown by the broken lines in FIG. 2 and the time of the double selected state of the word line continues long. After the point Q, the discharging current IDC is supplied through the negative word line 2 changing from the non selected state to the selected state.
Thus, although the word line discharging circuit 10 is provided in the circuit shown in FIG. 1, this word line discharging circuit 10 can only perform its function effectively till the point Q and after that the discharging speed is slowed down and the potential of the word line cannot be lowered rapidly.
As other prior art of interest to the present invention, the following documents (1) to (3) are known.
(1) U.S. Pat. No. 4,393,476
(2) ISSCC Dig. of Tech. Paper pp. 108-109, 1983 "A 15ns 16kb ECL TAM with a PNP Load Cell" by Kazuhiro Toyoda et al.
(3) ISSCC Dig. of Tech. Paper pp. 214-215, 1986 "A 3.5ns, 2W, 20mm.sup.2 16kb ECL Bipolar RAM" by Kunihiko Yamaguchi et al.
In the prior art document (1), there are provided, in addition to a current source for discharging of word lines, current sources for the respective word lines for the purpose of preventing saturation of the discharging transistors and, therefore, the circuit has a complicated configuration and a large size and the manufacturing cost thereof is high. In addition, since the current source provided for each word line is supplied with current from the word line through a diode, its operative range to power supply voltage is limited by a voltage drop in the diode.
According to the prior art documents (2) and (3), a word line discharging circuit is formed by capacitors C and resistors R in either document so that a prescribed amount of current is removed from a word line within a period of time determined by a time constant of CR when the word line concerned is in a non selected state. However, since the capacitance of the time constant circuit in either of those documents (2) and (3) is formed as a junction capacitance of a semiconductor device, it is difficult to set the capacitance to a certain value and the discharging time becomes too long or too short. In addition, there is another disadvantage that a large area is required to obtain a certain capacitance value, causing a semiconductor memory device to be large-sized.